1. Field of the Invention
The present invention relates to a semiconductor device, and relates in particular to a substrate potential generating circuit for an MIS (Metal Insulator Semiconductor) type semiconductor device.
In order to make the bias of the substrate in a semiconductor device negative, a substrate potential generating circuit (substrate bias generating circuit) is installed to pump the charge of the substrate into the Vss terminal according to charge pumping principles. In order to accomplish this, it is necessary to have a diode component, although the pn junction of the semiconductor device cannot itself be used as the diode. The reason for this is that when the charge is pumped out of the p-type substrate, a forward current is generated to inject electrons into the substrate. These electrons cause malfunctions such as destruction of the charge which is stored in the DRAM memory.
Thus, in the past, the diode component has been constructed using MOS transistors, as shown in FIGS. 4 and 5.
The substrate potential generating circuit shown in FIG. 4 is a circuit in which a p-channel MOS transistor is used as the diode component, and in which an oscillating circuit (1), capacitor element (2), p-channel MOS transistor (3), and p-channel MOS transistor (4) are connected as shown in the figure.
With this substrate potential generating circuit, the p-channel MOS transistor (4) and p-channel MOS transistor (3) function as diodes to pump the majority charge of the p-type substrate into the Vss terminal according to charge pumping principles, thereby providing the p-type semiconductor substrate with a negative bias.
The substrate potential generating circuit of FIG. 5 is a circuit in which the p-channel MOS transistor (4) of FIG. 4 is replaced by an n-channel MOS transistor (6). This circuit also pumps the majority charge of the p-type semiconductor substrate into the Vss terminal according to charge pumping principles to provide the substrate with a negative bias.
Typically a power source bias in the range of +5 V is applied in the substrate potential generating circuit shown in FIG. 4. In addition, the threshold value voltage V.sub.T of the p-channel MOS transistor (4) is in the range of 1.7 V. The potential at a node N1 is lowered to approximately -5 V by the oscillating circuit (1), although since the threshold value voltage V.sub.T of the p-channel MOS transistor (4) is in the range of 1.7 V, the potential of the node N1 is actually only lowered to approximately -3.3 V. In other words, the substrate potential generating circuit of FIG. 4 is unreliable in operation in that it has a shallow charge pumping depth which causes poor charge pumping efficiency, because the threshold value voltage V.sub.T of the p-channel MOS transistor (4) is high.
With the substrate potential generating circuit of FIG. 5, the threshold value voltage V.sub.T of the n-channel MOS transistor (6) is typically in the range of 0.4-0.5 V, and the pn junction forward voltage V.sub.F of the n-channel MOS transistor is in the range of 0.6 V. Thus, the threshold value voltage V.sub.T and the voltage V.sub.F are close to each other. As a result, when voltage fluctuations occur in the semiconductor device, minority carriers may be injected due to the competition occurring at the junction. These minority carriers when present may cause malfunctions such as a destruction of the data stored in a DRAM memory.
It is an object of the present invention to provide a substrate potential generating circuit in which a Schottky barrier diode is employed as the diode component of the substrate potential generating circuit to prevent injection of minority carriers into the substrate as charge is being pumped from the substrate.
Specifically, the substrate potential generating circuit of the present invention is constructed with the following: an oscillating circuit, a capacitor element which is connected to said oscillating circuit at a first contact point, a MOS transistor which is connected between a second contact point of said capacitor element and the reference potential of a semiconductor device, such as said terminal Vss, and a Schottky barrier diode, which is connected between the substrate of the semiconductor device and said second connecting point to face said second connecting point.
Since the Schottky barrier diode is operated by the majority carrier, the majority charge is directly pumped out of the p-type semiconductor device. Thus, it is possible to pump the hole charge with stability without injecting the minority charge, thus making it possible to provide the semiconductor substrate with a negative bias with stability.